1. Field of the Invention
The present invention relates to an output buffer circuit which is formed of semiconductor devices and particularly to an output buffer circuit which realizes voltage transition of a high speed output signal while generation of noise due to signal transition is suppressed.
2. Description of Related Art
In recent years, data processing velocity in an information processor such as a personal computer or the like is more and more improved and data transfer is executed via a high speed data bus such as PCI bus. Therefore, an output buffer circuit which is formed of semiconductor devices for driving these data buses is requested to drive the data bus in higher velocity. In order to drive data bus in higher velocity, it is required to transit in higher velocity a voltage level of the signal on the data bus and suppress erroneous detection of signal in the receiving side of the next stage such as over-shoot and under-shoot of voltage level due to the high speed voltage transition of signal and also to suppress disturbance of signal waveform which may result in noise to peripheral circuits. Therefore, it is required to control voltage transition characteristic of signal.
As the related art utilizing a circuit configuration which provides an output while controlling voltage transition of signal, the JP Laid-open Patent Publication No. 9-284111, for example, is disclosed. An output circuit of this circuit configuration is illustrated in FIG. 8. This output circuit includes at least a pull-up PMOS transistor 100 of the output stage, a plurality of pull-down NMOS transistors 200, 300 of the output stage respectively connected in the drains thereof to the drain of the pull-up PMOS100 and a drive circuit 2000 of the preceding stage for driving the pull-down NMOS transistors 200, 300 of the output stage.
The pull-down NMOS transistors 200, 300 of the output stage described above turn ON when the signal D becomes LOW level. Here, it should be noted that the gate of the pull-down NMOS transistor 200 of the output stage is driven with the signal D via a delay circuit 1000, a 3-input NAND900 and an inverter 800, while the gate of the NMOS transistor 300 of the output stage is driven with the signal D via the delay circuit 1000, 3-input NAND900, a delay circuit 1300, a 2-input NAND 1100 and an inverter 1400. Therefore, the NMOS transistor 300 turns ON after the NMOS transistor 200 turns ON. Thereby, a falling waveform of the output DOUT is rounded.
The output circuit of FIG. 8 of the related art is provided with a plurality of pull-down NMOS transistors 200, 300 of the output stage. In order to turn ON these transistors, the NMOS transistor 200 is turned ON first with a signal which is sequentially delayed and thereafter the NMOS transistor 300 is turned ON. Thereby, this configuration is capable of rounding a falling waveform of the output DOUT by switching over the driving capability.
However, since the driving capability is changed over by sequentially turning ON or OFF a plurality of pull-down NMOS transistors 200, 300 of the output stage, the current driving capability of the NMOS transistors as a whole in the ON state changes non-continuously after or before the NMOS transistors which are sequentially turned ON. In other words, a total sum of conductive resistance of NMOS transistors changes non-continuously. For example, in the case of configuration where two NMOS transistors of the same size are provided and these are sequentially turned ON, when the second NMOS transistors turns ON or OFF, the conductive resistance suddenly changes in the half or doubled changing rate.
Sudden change of current driving capability when the number of transistors of the output stage in the ON state is changed in the transit condition of voltage transition of signal and non-continuous change of conductive resistance depending on the change described above results in sudden change of characteristic impedance on a signal propagation path including an input impedance of the transmission line including data bus and the circuit in the receiving side of the next stage. Accordingly, there rises a fear for generation of disturbance of waveform such as over-shoot and under-shoot of the signal waveform. Disturbance of this signal waveform results in the problem that erroneous detection of signal is generated in the circuit of the receiving side or noise is also generated in the peripheral circuits.
Moreover, in order to suppress disturbance of signal waveform, voltage transition velocity of signal must be restricted. In this case, signal propagation velocity is restricted and thereby propagation delay is probably increased. In general, high speed operation in which propagation delay of signal is shortened is in the trade-off relationship to the stable operation in which disturbance of signal waveform such as over-shoot and under-shoot is suppressed and therefore it is requested to adjust both characteristics. It will become a problem if both characteristics cannot be adjusted under the condition that the high speed data transmission is more and more requested.